| Opcode/Instruction | Op/En | 64/32 bit Mode Support | CPUID Feature Flag | Description |
|---|---|---|---|---|
| EVEX.LLIG.NP.0F3A.W0 67 /r /ib VFPCLASSSH k1{k2}, xmm1/m16, imm8 | A | V/V | AVX512-FP16 | Test the input for the following categories: NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result. |
| Op/En | Tuple | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
|---|---|---|---|---|---|
| A | Scalar | ModRM:reg (w) | ModRM:r/m (r) | imm8 (r) | N/A |
Description
This instruction checks the low FP16 value in the source operand for special categories, specified by the set bits in the imm8 byte. Each set bit in imm8 specifies a category of floating-point values that the input data element is clas-sified against; see Table 5-8 for the categories. The classified results of all specified categories of an input value are ORed together to form the final boolean result for the input element. The result is written to the low bit in the desti-nation mask register according to the writemask. The other bits in the destination mask register are zeroed.
Operation
VFPCLASSSH dest{k2}, src, imm8
IF k2[0] or *no writemask*:
DEST.bit[0] := check_fp_class_fp16(src.fp16[0], imm8)
// see VFPCLASSPH
ELSE:
DEST.bit[0] := 0
DEST[MAXKL-1:1] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VFPCLASSSH __mmask8 _mm_fpclass_sh_mask (__m128h a, int imm8);
VFPCLASSSH __mmask8 _mm_mask_fpclass_sh_mask (__mmask8 k1, __m128h a, int imm8);
SIMD Floating-Point Exceptions
None.
Other Exceptions
EVEX-encoded instructions, see Table 2-58, “Type E10 Class Exception Conditions.”