| Opcode | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| 9B DD /7 | FSTSW m2byte | Valid | Valid | Store FPU status word at m2byte after checking for pending unmasked floating-point exceptions. |
| 9B DF E0 | FSTSW AX | Valid | Valid | Store FPU status word in AX register after checking for pending unmasked floating-point exceptions. |
| DD /7 | FNSTSW1 m2byte | Valid | Valid | Store FPU status word at m2byte without checking for pending unmasked floating-point exceptions. |
| DF E0 | FNSTSW1 AX | Valid | Valid | Store FPU status word in AX register without checking for pending unmasked floating-point exceptions. |
NOTES:
1. See IA-32 Architecture Compatibility section below.
Stores the current value of the x87 FPU status word in the destination location. The destination operand can be either a two-byte memory location or the AX register. The FSTSW instruction checks for and handles pending unmasked floating-point exceptions before storing the status word; the FNSTSW instruction does not.
The FNSTSW AX form of the instruction is used primarily in conditional branching (for instance, after an FPU comparison instruction or an FPREM, FPREM1, or FXAM instruction), where the direction of the branch depends on the state of the FPU condition code flags. (See the section titled “Branching and Conditional Moves on FPU Condition Codes” in Chapter 8 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.) This instruction can also be used to invoke exception handlers (by examining the exception flags) in environments that do not use interrupts. When the FNSTSW AX instruction is executed, the AX register is updated before the processor executes any further instructions. The status stored in the AX register is thus guaranteed to be from the completion of the prior FPU instruction.
The assembler issues two instructions for the FSTSW instruction (an FWAIT instruction followed by an FNSTSW instruction), and the processor executes each of these instructions separately. If an exception is generated for either of these instructions, the save EIP points to the instruction that caused the exception.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
When operating a Pentium or Intel486 processor in MS-DOS compatibility mode, it is possible (under unusual circumstances) for an FNSTSW instruction to be interrupted prior to being executed to handle a pending FPU excep-tion. See the section titled “No-Wait FPU Instructions Can Get FPU Interrupt in Window” in Appendix D of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for a description of these circumstances. An FNSTSW instruction cannot be interrupted in this way on later Intel processors, except for the Intel QuarkTM X1000 processor.