| Opcode/Instruction | Op/En | 64/32-bit Mode | CPUID Feature Flag | Description |
|---|---|---|---|---|
| 66 0F 38 DB /r AESIMC xmm1, xmm2/m128 | RM | V/V | AES | Perform the InvMixColumn transformation on a 128-bit round key from xmm2/m128 and store the result in xmm1. |
| VEX.128.66.0F38.WIG DB /r VAESIMC xmm1, xmm2/m128 | RM | V/V | Both AES and AVX flags | Perform the InvMixColumn transformation on a 128-bit round key from xmm2/m128 and store the result in xmm1. |
| Op/En | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
|---|---|---|---|---|
| RM | ModRM:reg (w) | ModRM:r/m (r) | N/A | N/A |
Perform the InvMixColumns transformation on the source operand and store the result in the destination operand. The destination operand is an XMM register. The source operand can be an XMM register or a 128-bit memory loca-tion.
Note: the AESIMC instruction should be applied to the expanded AES round keys (except for the first and last round key) in order to prepare them for decryption using the “Equivalent Inverse Cipher” (defined in FIPS 197).
128-bit Legacy SSE version: Bits (MAXVL-1:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: Bits (MAXVL-1:128) of the destination YMM register are zeroed.
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
AESIMC
DEST[127:0] := InvMixColumns( SRC ); DEST[MAXVL-1:128] (Unmodified)
VAESIMC
DEST[127:0] := InvMixColumns( SRC ); DEST[MAXVL-1:128] := 0;
(V)AESIMC __m128i _mm_aesimc (__m128i)
None.
See Table 2-21, “Type 4 Class Exception Conditions,” additionally:
| #UD | If VEX.vvvv ≠ 1111B. |